The present invention relates to emitter function logic gates and, in particular, to such gates having complementary outputs.
Emitter function logic is a class of logic circuit developed for use in large scale integration (LSI) fabrication. Emitter function logic uses less area than other logic circuits by providing only a true output, and not a complementary output. Thus, the requirement of complementing a signal twice to provide a true output as in other logic families is avoided. Therefore, emitter function logic (EFL) is limited to gates which do not require both a true and complementary output. However, by reducing the Miller effect (the multiplication of collector-base feedback capacitance by the voltage gain) and replacing a passive emitter-follower with an active emitter-follower, EFL enjoys an improved speed-power product over ECL (emitter-coupled logic). Modifications of EFL gates to provide complementary outputs have been created, but there is a time delay between the appearance at the output of the true output and the complementary output, thereby limiting the applications.
FIG. 1 shows a basic EFL AND gate 10 as disclosed in U.S. Pat. No. 3,795,822 to Skokan. AND gate 10 has first and second inputs 12 and 14, respectively. Inputs 12 and 14 are coupled to the first and second emitters of an input transistor 16. The base of transistor 16 is coupled to a reference voltage 18 and its collector is coupled through a resistor 20 to a supply voltage 22. The collector of transistor 16 is also coupled to the base of an output transistor 24. The collector of output transistor 24 is also coupled to supply voltage 22. Transistor 24 has an emitter coupled to an output 26 which provides the output of the AND gate. Output 26 is a true output, and no complementary output is provided. Resistor 20 provides biasing and a transistor 28 prevents saturation of output transistor 24.
A modified EFL circuit with latched true and complementary outputs is shown in FIG. 2 as disclosed in U.S. Pat. No. 4,145,623 to Doucette. Latch 30 of FIG. 2 uses an input transistor 32 which has its base coupled to a data input 34. Its emitter is coupled to a first emitter 36 of a transistor 38, which is similar to transistor 16 of FIG. 1. Transistor 38 has a collector which provides a true output 40 and is also coupled to the base of an output transistor 42. The collector of output transistor 42 is coupled to the collector of input transistor 32 and provides a complementary output 44. The collectors of transistors 38 and 42 are coupled to a supply voltage 46 through resistors 48 and 50 respectively. A clock input 52 is provided to the base of a transistor 54 which is coupled at its emitter to another transistor 56. The base of transistor 56 is coupled to a voltage reference 58. The coupled emitters of transistors 54 and 56 are coupled to a current source 60. The clock serves to latch the outputs on true and complementary outputs 40 and 44, respectively.
Although gate 30 provides both true and complementary outputs, it can be seen from an examination of the circuit that signals will appear at these outputs at different periods of time after an input is applied to data input 34. The true signal on output 40 will not change state until the input signal propagates through transistor 32 and transistor 38. The propagation time through transistor 38 is the turn-on time of the transistor. The turn-on time is small because it is a minimum geometry device, the capacitive effects are relatively small and its base is at a constant reference D.C. voltage. The complementary output 44 will not change state, however, until the signal additionally propagates through transistor 42. Thus, the time at which outputs appear on the true and complementary outputs varies by an amount equal to the propagation delay through one transistor stage.
In certain applications, it is desirable to have concurrent true and complementary outputs from an EFL gate without compromising the size and speed advantages of the EFL gate.